1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly to a nonvolatile semiconductor memory device integrated on a common same semiconductor substrate (chip) with a logic circuit such as a processor. More specifically, the present invention relates to a construction for reducing power consumption and occupying area of the nonvolatile semiconductor memory device and for reading data at high speed.
2. Description of the Background Art
Semiconductor memory devices that store information in a nonvolatile manner include a flash memory. In the flash memory, a memory cell is formed of one stacked gate field effect transistor (memory cell transistor) having a floating gate. An electric field is applied to the floating gate to perform injection/extraction of electric charges (electrons) on the floating gate through an F-N (Fowler-Nordheim) tunneling phenomenon or a Channel Hot Electron phenomenon, for changing a threshold voltage of the memory cell transistor. For different threshold voltages of the memory cell transistor, different amounts of current flow through the memory cell upon selection of the memory cell, to store data according to the amount of current. In the case where an n-channel transistor is used for the memory cell transistor, a state in which electrons are injected into the floating gate is a state in which the threshold voltage is high, while a state in which the electrons are extracted from the floating gate is a state in which the threshold voltage is low. According to the quantity of accumulated electric charges (quantity of accumulated electrons) at this floating gate, a state in which a current starts to flow when the gate voltage is set to set to 6.5 V or higher and a state in which a current flows when the gate voltage is even at 4.0 V can be implemented. Accordingly, when the gate voltage is set to an intermediate voltage of, for example, 5.0 V in reading data, the state in which the current flows and the state in which substantially no current flows through the memory cell transistor are discriminated. The state of the memory cell data can be identified to read out data by sensing the amount of current flowing the memory cell transistor.
When the injection/extraction of electrons is performed on the floating gate to store data, a problem of “over-erasure” needs to be considered. The “over-erasure” represents a state in which the electrons are excessively extracted from the floating gate (in the case where the memory cell transistor is an n-channel transistor), rendering the threshold voltage 0.0 V or lower, and accordingly, a current flows even when the memory cell is in a non-selected state, that is, a state similar to a so-called depletion state of an MOS transistor (insulated gate field effect transistor). Normally, in reading data, a gate potential of a selected memory cell transistor is set to an intermediate potential, while a non-selected memory cell has a gate potential of kept at 0.0 V and is set to a state of causing no current flow in a normal state. In reading data, the current flowing through the selected memory cell is sensed by a sense amplifier. However, when the non-selected memory cell is in the over-erasure state, the current flows through this non-selected memory cell, and, there arises a problem that the data is determined based on a combined current of the selected memory cell and the non-selected memory cell in the over-erasure state in the sense amplifier, resulting in erroneous reading.
In the memory cell transistor, there is variation in physical property such as film thickness and film quality due to variation in manufacturing parameter during the manufacturing process, and accordingly, there arises variation in electric characteristics, extraction/injection speeds of electrons for the floating gate vary within a certain range. Thus, when the electrons are extracted from the floating gate to set a threshold voltage to a low state, there is possibility that a memory cell transistor from which the electrons are excessively extracted is produced even under the same voltage applying condition, so that the memory cell transistor in the over-erasure state is present. Consequently, in order to prevent such over-erasure, the threshold voltage of the memory cell transistor can not be set sufficiently low, and thus, the problem arises that the data cannot be read under a low power supply voltage.
In order to avoid such over-erasure, the distribution of the threshold voltages needs to be precisely controlled by performing erasure verification in writing data. However, when the erasure verification operation is performed for each bit to control the threshold voltage distribution, the processing takes a long time and the processing sequence becomes complicated, which causes a problem that high speed data writing/erasure cannot be achieved. Furthermore, the complexity of the erasure verification sequence leads to an increased cost and becomes an obstacle against achieving a low cost memory device.
In order to solve the above-described problem of over-erasure, a construction in which a cell structure of EEPROM (Electronically Erasable and Programmable Read Only Memory) is utilized is disclosed in Prior Art Document 1 (Japanese Patent Laying-Open No. 2001-015617). In the construction shown in Prior Art Document 1, a memory cell transistor is formed of a stacked gate field effect transistor, and a selection transistor is connected to the memory cell transistor in series. A source node of the memory cell transistor is coupled to a source line. In reading data, the selection transistor is made conductive and the memory cell transistor is coupled to a bit line to form a path for causing a current flow between the bit line and the source line. As for a non-selected memory cell, the selection transistor is in a non-conductive state, and even if the memory cell transistor is in an over-erasure state, the non-selected memory cell is isolated from the bit line, so that the current flowing path between the bit line and the source line is shut off. Accordingly, the non-selected memory cell, even in the over-erasure state, can be prevented from influencing the reading current of the selected memory cell. In Prior Art Document 1, stacked gate layers formed in the same manufacturing steps as those of the floating gate and a control gate of the memory cell transistor are used as a control electrode (selection gate), and these electrode layer corresponding to the control gate and electrode layer corresponding to the floating gate are electrically shorted to equivalently implement a single gate MOS transistor.
In the case where the flash memory cell structure is utilized, in order to avoid the problem of over-erasure, the threshold voltage cannot be sufficiently reduced. Accordingly, in selecting a memory cell, a voltage level applied to the control gate needs to be internally boosted in a positive or negative direction, and thus, an external power supply voltage (non-boosted) cannot be utilized without conversion, which causes a problem of an increase in power consumption. Furthermore, a charge pump circuit for boosting needs to be internally provided, which causes a problem of an increase in chip area.
When a gate potential of a selected memory cell is set using a boosting pump, the data cannot be read until the boosted voltage becomes stable, and thus, high speed data reading cannot be achieved. Furthermore, when the capacity of the boosting pump is insufficient, there arises a problem that the amount of current consumed in memory cell selection cannot be sufficiently compensated for, and that thus, the boosted voltage cannot be stably generated and supplied, so that the memory cells cannot be successively selected for reading data.
As disclosed in Prior Art Document 1, in the case where the memory cell structure is comprised of a series body of a stacked gate field effect transistor and a selection transistor, the problem of the over-erasure can be avoided even when the threshold voltage of the stacked gate field effect transistor is set low. In the memory cell structure disclosed in Prior Art Document 1, the selection transistor is equivalently formed of a single gate MOS transistor. Accordingly, when the memory cell transistor formed of the stacked gate field effect transistor is coupled to a corresponding bit line, in order to reliably cause current amount change on the bit line according to the storage data of the memory cell without being influenced by the threshold voltage of the selection transistor, it is necessary to render the gate voltage of the selection transistor high for transmitting, to the memory cell transistor, the reading voltage supplied to the bit line without threshold voltage loss and without voltage drop by its channel resistance.
In Prior Art Document 1, in a logic merged device with the memory device and a logic circuit being integrated on a common chip, in order to avoid the aluminum penetration of the electrode interconnection line which may caused when the selection transistor is implemented using the gage electrode layer the same as the floating gate to make the gate electrode thickness of the selection transistor thin for achieving the flattening of the logic merged device, the interconnection lines of the same layers as the control gate layer and the floating gate layer of the stacked gate field effect transistor are used and are shorted with each other. In Prior Art Document 1, no consideration is given to neither the problem associated with the gate potential of the selection transistor nor the electrical characteristics such as current dissipation.